The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.
An essential component of any silicon validation program is the capability to quickly and efficiently reproduce system failures on the RTL model (register-transfer level model) of the chip under test, in the case of a logic issue, or on the tester, in the case of a circuit issue. The major problem of reproduction is to ensure that silicon behavior on the system is absolutely synchronized with that of the RTL model tester. This is because most failures occur far beyond the reset point. The reset point presents a known state, for example, at the beginning of test, but information within the processor arrays and registers (e.g., caches, TLBs (Translation lookaside buffers), branch predictors, etc.), change during the course of the test, and differ at the failure point from the reset point. With conventional mechanisms, a “dump” of many, but not all, information states is available at the failure point, but it is completely unknowable what the information states are for intermediate periods between the start of test and the failure point.
Debugging post-silicon system failures within guaranteed time duration is a major challenge. Even with increasing focus on debug methods, it still requires several experts to be available for the duration of the debug. The experts themselves are rare resource due to their skill set, and thus, sufficient expert resources may be unobtainable to debug all errors during an acceptable period of time.
Improved visibility and debug methodologies and tools are needed to improve debug times, reduce the level of expertise needed to perform post-silicon system failures, and improve the capability to diagnose and root case failures.
The present state of the art may therefore benefit from systems and methods for implementing and using PSMI using at-speed scan capture as described herein.